Most electronic systems include a number of networked elements (components) such as hardware and software that form the system. In most systems there is a layer responsible for communication between the different components that form a networked element as well as between the different networked elements themselves. This layer is typically referred to as the InterProcessor Communication (IPC) layer.
Several protocols have been introduced in the last few years to deal with interprocessor communications. One example of an IPC product is PCI AGP Controller (PAC) that integrates a Host-to-PCI bridge, Dynamic Random Access Memory (DRAM) controller and data path and an Accelerated Graphics Port (AGP) interface. Another example of an IPC product is the OMAP™ platforms. Neither of these platforms provide much if any support above the hardware level and provide little design flexibility at the lower level component or channel levels (physical layer).
The PAC platforms for example, are closed architectures and are embedded into the Operating System's TAPI layer, with the IPC code not being accessible to developers. Therefore, these platforms do not extend to the component levels and they also do not allow for dynamic assignment of IPC resources, hardware support capabilities, or multi-node routing, etc. as well as not allowing for the dynamic assignment of the IPC resources. With the need for lower power consumption and less system latencies, a need exists in the art for an IPC network that can provide for intelligent targeting of IPC nodes so that there is less wasted time and less power consumption when looking for a processor in the IPC system that can provide a needed service.